A description will be given of a conventional compound semiconductor integrated circuit device by using a GaAs integrated circuit device (referred to as a GaAsIC hereinafter) as one example.
FIG. 5 is a sectional view showing an example of a conventional GaAsIC with a part between elements in the center thereof. In FIG. 5, reference numeral 1 designates a semi-insulating GaAs substrate, reference numeral 2 designates an n type GaAs layer formed on the semi-insulating GaAs substrate 1 by epitaxial growth, reference numeral 16 designates a hydrogen ion implantation region formed in the n type GaAs layer 2 and the semi-insulating GaAs substrate 1 to isolate elements, reference numerals 5 and 6 designate field effect transistors (referred to as FET's hereinafter) formed in the GaAsIC, reference numerals 7 and 10 designate source electrodes of the FET's 5 and 6, respectively, reference numerals 8 and 11 designate gate electrodes of the FET's 5 and 6, respectively, and reference numerals 9 and 12 designate drain electrodes of the FET's 5 and 6, respectively.
FIGS. 6(a)-6(c) are sectional views showing an example of manufacturing flow to manufacture the GaAsIC shown in FIG. 5. The manufacturing flow will be described hereinafter.
First, as shown in FIG. 6(a), the n type GaAs layer (n layer) 2 is formed on the semi-insulating GaAs substrate 1 by epitaxial growth.
Then, as shown in FIG. 6(b), a desired amount of hydrogen ions are implanted between the element 5 and the element 6 (which are FET's in this case) to form a hydrogen ion implantation region 16. The resistance of the n type GaAs layer 2 in this hydrogen ion implantation region 16 is increased because carrier trapping centers are formed by ion implantation, so that this layer serves as a semi-insulating layer (i layer), whereby element isolation can be implemented.
Then, the source electrodes 7 and 10, the gate electrodes 8 and 11, and the drain electrodes 9 and 12 are formed in the FET's 5 and 6, respectively and these are wired. Thus, the GaAsIC is completed.
Isolation between elements is implemented in the conventional GaAsIC through the above-described manufacturing flow. A curve 13 shown in FIG. 3 shows an example of the voltage-current characteristic between elements in this case. When a voltage between elements is less than V.sub.TF1 (called as a trap fill voltage), an ohmic current flows and resistance between elements is high. When it is more than V.sub.TF1, current is abruptly increased and then resistance between the elements is also abruptly reduced, whereby leakage current is increased.
In addition, when a voltage of V.sub.TF1 or more is applied between the elements, as a phenomenon particular to a compound semiconductor having a semi-insulating characteristic, a back gate effect, is generated by breakdown of the n-i-n structure and the isolated elements ar mutually influenced, with the result that characteristics of the elements are lowered.
Furthermore, there is the negative correlation between the above described trap fill voltage V.sub.TF1 and the resistance in the ohmic region in general as shown in FIG. 9. When the resistance in the ohmic region is increased by adjusting the implantation condition of hydrogen ions, the voltage V.sub.TF1 is reduced and then the back gate effect is likely to be generated, with the result that it is not possible to keep both at appropriate values.
As described above, since it is not possible to keep both the resistance between elements and the trap fill voltage high in the conventional compound semiconductor integrated circuit device, the element characteristics are lowered because the leakage current is large or the elements are mutually influenced by the breakdown.